FPGA-Implemented Fractal Decoder with Forward Error Correction in Short-Reach Optical Interconnects

Forward error correction (FEC) codes combined with high-order modulator formats, i.e., coded modulation (CM), are essential in optical communication networks to achieve highly efficient and reliable communication. The task of providing additional error control in the design of CM systems with high-performance requirements remains urgent. As an additional control of CM systems, we propose to use indivisible error detection codes based on a positional number system. In this work, we evaluated the indivisible code using the average probability method (APM) for the binary symmetric channel (BSC), which has the simplicity, versatility and reliability of the estimate, which is close to reality. The APM allows for evaluation and compares indivisible codes according to parameters of correct transmission, and detectable and undetectable errors. Indivisible codes allow for the end-to-end (E2E) control of the transmission and processing of information in digital systems and design devices with a regular structure and high speed. This study researched a fractal decoder device for additional error control, implemented in field-programmable gate array (FPGA) software with FEC for short-reach optical interconnects with multilevel pulse amplitude (PAM-M) modulated with Gray code mapping. Indivisible codes with natural redundancy require far fewer hardware costs to develop and implement encoding and decoding devices with a sufficiently high error detection efficiency. We achieved a reduction in hardware costs for a fractal decoder by using the fractal property of the indivisible code from 10% to 30% for different n while receiving the reciprocal of the golden ratio.

PresB-Net: parametric binarized neural network with learnable activations and shuffled grouped convolution

In this study, we present a novel performance-enhancing binarized neural network model called PresB-Net: Parametric Binarized Neural Network. A binarized neural network (BNN) model can achieve fast output computation with low hardware costs by using binarized weights and features. However, performance degradation is the most critical problem in BNN models. Our PresB-Net combines several state-of-the-art BNN structures including the learnable activation with additional trainable parameters and shuffled grouped convolution. Notably, we propose a new normalization approach, which reduces the imbalance between the shuffled groups occurring in shuffled grouped convolutions. Besides, the proposed normalization approach helps gradient convergence so that the unstableness of the learning can be amortized when applying the learnable activation. Our novel BNN model enhances the classification performance compared with other existing BNN models. Notably, the proposed PresB-Net-18 achieves 73.84% Top-1 inference accuracy for the CIFAR-100 dataset, outperforming other existing counterparts.

Computer System for Converting Gestures to Text and Audio Messages

Today, there are quite a large number of deaf- mute and hard-of-hearing people which communicate using gestures. Therefore, it is simply necessary to provide them with modern means of communication with the surrounding world. This paper creates a holistic computer system architecture for converting gestures into text and audio messages. The principles of construction and basic design solutions of a computer system based on a modern element base with increased productivity and minimization of hardware costs and energy consumption have been developed. The most popular existing solutions for gesture recognition are considered and analyzed. The operation of the main components has been described, the principle of functioning of the entire system has been analyzed, and their advantages and disadvantages have been compared. The latest structural components for building a computer system (both physical and software) have been selected and investigated. Physical features include: the state-of-the-art Arduino Nano computing platform, the HC-05 Bluetooth module, the ADXL335 accelerometer, and the latest ZD10-100 Information sensor (flexibility sensor). Software features include: firmware for the Arduino Nano hardware platform, Python-based software for splitting the flow of letters into words, displaying them, and voicing them. The methods of Google Media Translation API and Google Text-to-speech (gTTS) have been analyzed. The expediency of conducting research has improved performance through the use of a new information sensor, which is a flexibility sensor ZD10-100 500 g. The general structural scheme of all systems has been designed.

Structures of processors for calculating the instant Walsh spectrum

The work is devoted to the development of circuits for fast Walsh transform processors of the serialparallel type. The fast Walsh transform processors are designed for decoding error-correcting codes and synchronization; their use can reduce the cost of calculating the instantaneous Walsh spectrum by almost 2 times. The class of processors for computing the instantaneous spectrum according to Walsh is called serialparallel processors. Circuits of the fast Walsh transform processors of serial-parallel type have been developed. A comparative analysis of the constructed graphs of the fast Walsh transform processors is carried out. A method and a processor for calculating the Walsh transform coefficients are proposed, which allows increasing the speed of the transformations performed. When calculating the conversion coefficients using processors of parallel, serial and serial-parallel types, it was found that controllers of the serial-parallel type require 2(N–1) operations when calculating the instantaneous spectrum according to Walsh. The results obtained can be used in the design of discrete information processing devices, in telecommunication systems when coding signals for their noise-immune transmission and decoding, which ensures the optimal number of operations, and therefore the optimal hardware costs.

An Efficient Interconnection System for Neural NOC Using Fault Tolerant Routing Method

Large scale Neural Network (NN) accelerators typically have multiple processing nodes that can be implemented as a multi-core chip, and can be organized on a network of chips (noise) corresponding to neurons with heavy traffic. Portions of several NoC-based NN chip-to-chip interconnect networks are linked to further enhance overall nerve amplification capacity. Large volumes of multicast on-chip or cross-chip can further complicate the construction of a cross-link network and create a NN barrier of device capacity and resources. In this paper, this refer to inter-chip and inter-chip communication strategies known as neuron connection for NN accelerators. Interconnect for powerful fault-tolerant routing system neural NoC is implemented in this paper. This recommends crossbar arbitration placement, virtual interrupts, and path-based parallelization strategies in terms of intra-chip communications for the virtual channel routing resulting in higher NoC output at lower hardware costs. A lightweight NoC compatible chip-to-chip interconnection scheme is proposed regarding to inter-chip communication for multicast-based data traffic to enable efficient interconnection for NoC-based NN chips. Moreover, the proposed methods will be tested with four Field Programmable Gate Arrays (FPGAs) on four hard-wired deep neural network (DNN) chips. From the experimental results it can be illustrate that a high throguput can obtained effectively by the proposed interconnection network in handling thedata traffic and low DNN through advanced links.

FAILURE TOLERANT SYNCHRONOUS AND SELT-TIED CIRCUITS COMPARISON

The article considers the problem of developing synchronous and self-timed (ST) digital circuits that are tolerant to soft errors. Synchronous circuits traditionally use the 2-of-3 voting principle to ensure single failure, resulting in three times the hardware costs. In ST circuits, due to dual-rail signal coding and two-phase control, even duplication provides a soft error tolerance level 2.1 to 3.5 times higher than the triple modular redundant synchronous counterpart. The development of new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for the electronic circuits' failure tolerance

Application of non-positional representation of information in environmental monitoring systems

Developing forward-looking and advanced information systems requires the creation of a unified architecture, with unified hardware and software based on comprehensive integration of components of natural and technical information systems not only at the technical, but also at the functional level, The implementation of the above structure leads to a multiple increase in the volume of calculations on large-bit data arrays carried out in real time, as well as to the complexity of computational algorithms. It results in sharp contradictions between hardware costs, speed, accuracy and fault tolerance. The work is concerned with the formation of a methodology for the probabilistic representation and information transformation and the development on its basis of techniques, methods and algorithms for the synthesis of computing devices and components for advanced and existing information systems built on the domestic element base, which becomes an effective and high-tech means of overcoming these contradictions.

DETECTING AND CORRECTING BYTE ERRORS IN DIGITAL DATA TRANSMISSION SYSTEMS

Обоснована необходимость разработки методического аппарата, связанного с построением кода, корректирующего ошибки в заданном числе байтов информации с алгебраическим синдромным декодированием и оценкой аппаратурных и временных затрат, связанных с этой целью. Представлены правила построения корректирующего кода, исправляющего ошибки в заданном числе байтов информации, реализующего линейную процедуру построения корректирующего кода с синдромным декодированием и использованием аддитивного вектора ошибок, что позволило сократить аппаратурные затраты на построение декодирующего устройства (сократить объем памяти для хранения значений векторов ошибок). Получены выражения для оценки аппаратурных затрат на кодирование и декодирование информации при использовании предлагаемого метода коррекции пакетных ошибок. The necessity of developing a methodological apparatus related to the construction of a code that corrects errors in a given number of bytes of information with algebraic syndrome decoding and the estimation of hardware and time costs associated with this purpose is justified. The rules for constructing a correction code that corrects errors in a given number of bytes of information, implementing a linear procedure for constructing a correction code with syndrome decoding and using an additive error vector, are presented. This method made it possible to reduce the hardware costs for constructing a decoding device (reducing the amount of memory for storing the values of error vectors). Expressions are obtained for estimating the hardware costs of encoding and decoding information when using the proposed method of correcting packet errors.

Evaluation of different quantization resolution levels on the BER performance of massive MIMO systems under different operating scenarios

The massive MIMO system is one of the main technologies in the fifth generation (5G) of telecommunication systems, also recognized as a highly large-scale system. Constantly in massive MIMO systems, the base station (BS) is provided with a large number of antennas, and this large number of antennas need high-quantization resolution levels analog-to-digital converters (ADCs). In this situation, there will be more power consumption and hardware costs. This paper presents the simulation performance of a suggested method to investigate and analyze the effects of different quantization resolution levels of ADCs on the bit error rate (BER) performance of massive MIMO system under different operating scenarios using MATLAB software. The results show that the SNR exceeds 12 dB accounts for only 0.001% of BER signals when the number of antennas 60 with low quantization a 2 bits’ levels ADCs, approximately. But when the antenna number rises to 300, the SNR exceeds 12 dB accounts for almost 0.01% of BER transmitted signals. Comparably with the BER performance of high quantization, 4 bits-quantization resolution levels ADCs with the same different antennas have a slight degradation. Therefore, the number of antennas is a very important influence factor.

The Iron-Age of Storage Batteries: Techno-Economic Promises and Challenges

In this article, we explore the techno-economic promises and challenges related to iron electrode systems, specifically in the iron-air system. We study the discharge-charge products of an iron-air system in an aqueous electrolyte using an iron-water Pourbaix diagram. Using the discharge-charge products from the Pourbaix analysis, we construct a proposed baseline iron-air cell to estimate the basic voltage and capacity of the cell. This cell is then assembled into a battery pack to analyze the unit cost of a 150-hour iron-air system using a process-based cost model developed from the BatPaC model. With the appropriate choice of materials for an iron-air system, we estimate the total battery pack system cost for iron-air to be about US$25/kWh where the cell material costs are around US$5/kWh. The pack hardware costs, air delivery system, and manufacturing costs together account for over US$20/kWh. Through further engineering improvements, better catalysts, and cell chemistry improvements, the battery pack costs may be reduced further, which is promising for long-duration storage applications.