scholarly journals Graded Crystalline HfO₂ Gate Dielectric Layer for High-k/Ge MOS Gate Stack

2021 ◽  
Vol 9 ◽  
pp. 295-299
Author(s):  
Chan Ho Lee ◽  
Jeong Yong Yang ◽  
Junseok Heo ◽  
Geonwook Yoo
Keyword(s):  
Dielectric Layer ◽  
Gate Dielectric ◽  
Gate Stack ◽  
High K ◽  
Mos Gate

scholarly journals Impact of Hydrogen Bonds Limited Dipolar Disorder in High-k Polymer Gate Dielectric on Charge Carrier Transport in OFET

Polymers ◽  
2020 ◽  
Vol 12 (4) ◽  
pp. 826
Author(s):  
Bartosz Paruzel ◽  
Jiří Pfleger ◽  
Jiří Brus ◽  
Miroslav Menšík ◽  
Francesco Piana ◽  
...  
Keyword(s):  
Hydrogen Bonds ◽  
Charge Carrier ◽  
Charge Transport ◽  
Density Of States ◽  
Dielectric Layer ◽  
Carrier Transport ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Semiconductor Layer ◽  
High K

The paper contributes to the characterization and understanding the mutual interactions of the polar polymer gate dielectric and organic semiconductor in organic field effect transistors (OFETs). It has been shown on the example of cyanoethylated polyvinylalcohol (CEPVA), the high-k dielectric containing strong polar side groups, that the conditions during dielectric layer solidification can significantly affect the charge transport in the semiconductor layer. In contrast to the previous literature we attributed the reduced mobility to the broader distribution of the semiconductor density of states (DOS) due to a significant dipolar disorder in the dielectric layer. The combination of infrared (IR), solid-state nuclear magnetic resonance (NMR) and broadband dielectric (BDS) spectroscopy confirmed the presence of a rigid hydrogen bonds network in the CEPVA polymer. The formation of such network limits the dipolar disorder in the dielectric layer and leads to a significantly narrowed distribution of the density of states (DOS) and, hence, to the higher charge carrier mobility in the OFET active channel made of 6,13-bis(triisopropylsilylethynyl)pentacene. The low temperature drying process of CEPVA dielectric results in the decreased energy disorder of transport states in the adjacent semiconductor layer, which is then similar as in OFETs equipped with the much less polar poly(4-vinylphenol) (PVP). Breaking hydrogen bonds at temperatures around 50 °C results in the gradual disintegration of the stabilizing network and deterioration of the charge transport due to a broader distribution of DOS.

Challenges in Integrating the High-K Gate Dielectric Film to the Conventional Cmos Process Flow

2001 ◽  
Vol 670 ◽  
Author(s):  
Avinash Agarwal ◽  
Michael Freiler ◽  
Pat Lysaght ◽  
Loyd Perrymore ◽  
Renate Bergmann ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Film ◽  
Cmos Process ◽  
Gate Stack ◽  
Process Flow ◽  
High K ◽  
High K Materials ◽  
Wet Etch ◽  
The Impact ◽  
High K Gate Dielectric

ABSTRACTZrO2 and HfO2 and their alloys with SiO2 are currently among the leading high-k materials for replacing SiOxNy as the gate dielectric for the sub-100 nm technology nodes. International SEMATECH (ISMT) is currently investigating integration issues associated with this required change in materials. Our work has focused on the integration of ALCVD deposited ZrO2 and HfO2 with an industry standard conventional MOSFET process flow with poly-Si electrode. Since the impact of contamination by these new high-k materials introduced in a production fab has not yet been established, it becomes very critical to prevent cross- contamination through the process tools in the fab. A baseline study was completed within ISMT's fab and appropriate protocols for handling high-k materials have been established. The integrated high-k gate stack in a conventional transistor flow should not only meet all the performance requirements of scaled transistors, but the gate dielectric film should be able withstand high-temperature anneal steps. Reactions between ZrO2 and Si have been observed at temperatures as low as 560°C (during the amorphous Si deposition process). Various wet chemistries were also evaluated for removing the high-k film inadvertently deposited on wafer backside, and it was found that ZrO2 etches at extremely slow rates in the majority of the common wet etch chemistries available in a fab. A new hot HF based process was found to be successful in lowering Zr contamination on the wafer backside to as low as 1.8 E10 atoms/cm2. The patterning of a high-k gate stack with poly-Si electrode is another area that required considerable focus. Various dry (plasma) etch and wet etch chemistries were evaluated for etching ZrO2 using both blanket films as well as wafers with patterned poly-Si gate over the high-k films. On the full CMOS flow device wafers, most of these wet chemistries resulted in severe pitting in the ZrO2 film remaining over the source/drain (S/D) areas, as well as in the Si substrate and the field oxide. A poly-Si gate over ZrO2 gate dielectric film was successfully patterned using the standard poly-Si gate etch (Cl2/HBr) for the main etch, followed by a combination of HF and H2SO4 clean for removing all of the ZrO2 remaining over the S/D area. This allowed the fabrication of low-resistance contacts to transistor S/D areas, which ultimately resulted in demonstration of functional transistors with high-k gate dielectric films.

High-k Materials for Advanced Gate Stack Dielectrics: a Comparison of ALCVD and MOCVD as Deposition Technologies

2003 ◽  
Vol 765 ◽  
Author(s):  
Matty Caymax ◽  
H. Bender ◽  
B. Brijs ◽  
T. Conard ◽  
S. DeGendt ◽  
...  
Keyword(s):  
Physical Vapor Deposition ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Dielectric Constants ◽  
Gate Stack ◽  
Interfacial Layers ◽  
High K ◽  
High K Materials ◽  
Gate Dielectric Material ◽  
Deposition Techniques

AbstractIn the quest for ever smaller transistor dimensions, the well-known and reliable SiO2 gate dielectric material needs to be replaced by alternatives whith higher dielectric constants in order to reduce the gate leakage. Candidate materials are metal oxides such as HfO2. Themost promising deposition techniques, next to Physical Vapor Deposition, appear to be ALCVD and MOCVD. In this paper, we compare the most important characteristics of layers from both proces techniques and assess their relevance to gate stack applications: density, crystallisation, impurities, growth mechanism, interfacial layers, dielectric constant, mobility. Although we find some minor differences, layers from both techniques mostly show striking similarities in many aspects, both positive and negative.

Electrical Characteristics of TaOxNy for High-k MOS Gate Dielectric Applications

2000 ◽  
Vol 611 ◽  
Author(s):  
Kiju Im ◽  
Hyungsuk Jung ◽  
Sanghun Jeon ◽  
Dooyoung Yang ◽  
Hyunsang Hwang
Keyword(s):  
Electron Spectroscopy ◽  
Gate Dielectric ◽  
Tantalum Oxide ◽  
Charge Trapping ◽  
Oxide Thickness ◽  
Electrical Characteristics ◽  
Equivalent Oxide Thickness ◽  
Ammonia Treatment ◽  
High K ◽  
Mos Gate

ABSTRACTIn this paper, we report a process for the preparation of high quality amorphous tantalum oxynitride (TaOxNy) via ammonia annealing of Ta2O5 followed by wet reoxidation for use in gate dielectric applications. Compared with tantalum oxide(Ta2O5), a significant improvement in the dielectric constant was obtained by the ammonia treatment followed by light reoxidation in a wet ambient. We confirmed nitrogen incorporation in the tantalum oxynitride (TaOxNy) by Auger Electron Spectroscopy. By optimizing the nitridation and reoxidation process, we obtained an equivalent oxide thickness of less than 1.6nm and a leakage current of less than 10mA/cm2 at -1.5V. Compared with NH3 nitridation, nitridation of Ta2O5 in ND3 improve charge trapping and charge-to-breakdown characteristics of tantalum oxynitride.

4H-SiC MOSFETs Using Thermal Oxidized Ta2Si Films as High-k Gate Dielectric

2005 ◽  
Vol 483-485 ◽  
pp. 713-716 ◽  
Author(s):  
Amador Pérez-Tomás ◽  
Phillippe Godignon ◽  
Narcis Mestres ◽  
Josep Montserrat ◽  
José Millan
Keyword(s):  
Dielectric Constant ◽  
Dielectric Layer ◽  
Room Temperature ◽  
Gate Dielectric ◽  
Gate Insulator ◽  
High K ◽  
Dry Oxidation ◽  
High K Dielectric ◽  
Si Films ◽  
Mis Capacitors

Oxidized Ta2Si layers have been used as high-k dielectric layer for 4H-SiC MOSFETs. The gate insulator was grown by dry oxidation of 40nm deposited Ta2Si during 1h at 1050oC. The dielectric constant obtained from 4H-SiC MIS capacitors is ~20 with an insulator thickness of 150nm. These devices exhibit adequate subthreshold, saturation and drive characteristics. For the MOSFETs fabricated on a p-implanted and annealed region, a peak mobility up to 45cm2/Vs has been extracted. The specific on-resistance of this device is 29mW·cm2 at room temperature with VDS=0.2V and VGS=14V.

Effects of Structural Properties of Hf-Based Gate Stack on Transistor Performance

2004 ◽  
Vol 811 ◽  
Author(s):  
G. Bersuker ◽  
J. H. Sim ◽  
C. D. Young ◽  
R. Choi ◽  
B. H. Lee ◽  
...  
Keyword(s):  
Cross Sections ◽  
Gate Dielectric ◽  
Electron Trapping ◽  
Gate Stack ◽  
Transistor Channel ◽  
High K ◽  
Grain Formation ◽  
Channel Effects ◽  
Different Origins ◽  
Capture Cross Sections

AbstractElectron traps in ALD and MOCVD HfO2 and HfSiO high-k dielectrics were investigated using both conventional DC and pulse measurements. It was found that the traps in the gate stack could be associated with defects of different activation energies and capture cross-sections. This points to potentially different origins of the electrically active defects, which can be either intrinsic or process-related. Structural non-uniformity of the high-k film, associated with grain formation and phase separation, may lead to variation of electrical properties of the gate dielectric along the transistor channel. Effects of such dielectric non-uniformity, as well as electron trapping, on the measured transistor mobility were evaluated.

Scalability of MOCVD-deposited Hafnium Oxide

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Van Elshocht ◽  
R. Carter ◽  
M. Caymax ◽  
M. Claes ◽  
T. Conard ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Process Conditions ◽  
Primary Concern ◽  
Gate Electrode ◽  
K Value ◽  
High K

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

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