Design of Robust Quantizers for Low-Bit Analog-to-Digital Converters for Gaussian Source

2019 ◽  
Vol 28 (supp01) ◽  
pp. 1940002 ◽  
Author(s):  
Milan R. Dinčić ◽  
Zoran H. Perić ◽  
Dragan B. Denić ◽  
Zoran Stamenković
Keyword(s):  
Energy Consumption ◽  
Communication Systems ◽  
Mimo Systems ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Analog To Digital Converters ◽  
Signal Power ◽  
Analog To Digital ◽  
Wide Range ◽  
Gaussian Source

This paper considers the design of robust logarithmic [Formula: see text]-law companding quantizers for the use in analog-to-digital converters (ADCs) in communication system receivers. The quantizers are designed for signals with the Gaussian distribution, since signals at the receivers of communication systems can be very well modeled by this type of distribution. Furthermore, linearization of the logarithmic [Formula: see text]-law companding function is performed to simplify hardware implementation of the quantizers. In order to reduce energy consumption, low-resolution quantizers are considered (up to 5 bits per sample). The main advantage of these quantizers is high robustness — they can provide approximately constant SNR in a wide range of signal power (this is very important since the signal power at receivers can vary in wide range, due to fading and other transmission effects). Using the logarithmic [Formula: see text]-law companding quantizers there is no need for using automatic gain control (AGC), which reduces the implementation complexity and increases the speed of the ADCs due to the absence of AGC delay. Numerical results show that the proposed model achieves good performances, better than a uniform quantizer, especially in a wide range of signal power. The proposed low-bit ADCs can be used in MIMO and 5G massive MIMO systems, where due to very high operating frequencies and a large number of receiving channels (and consequently a large number of ADCs), the reduction of ADC complexity and energy consumption becomes a significant goal.

Error Performance of Subsampling Digital Power Estimation for Integrated Receivers

2021 ◽  
Author(s):  
Aymen Khaleel ◽  
Ertan Zencir ◽  
Hasan Aksoy
Keyword(s):  
Automatic Gain Control ◽  
Estimation Error ◽  
Gain Control ◽  
Power Estimation ◽  
Building Blocks ◽  
Signal Power ◽  
Error Performance ◽  
Signal Simulation ◽  
Integrated Receivers ◽  
Integrated Receiver

Estimation of signal power levels at the output of integrated receiver building blocks is a vital function as the block voltage or power gains are set based on sensed power levels to maintain constant levels at block outputs in the receiver chain. RF and IF level real-time gain settings are determined with Automatic Gain Control (AGC) loops. AGC loop circuit topologies are usually based on analog detection circuits. These analog power detection circuits are based on techniques such as envelope detection, and logarithmic amplification usually accompanied by severe accuracy issues such as Process, Voltage and Temperature (PVT) spreads preventing correct gain adjustments. Adopting a dominantly digital approach to detect the signal power would ensure a significant reduction in PVT spreads. This work presents a review of the subsampling digital power estimation to create low power digital power estimations alternative to analog methods. The simulations of the method are applied to an AM and a 64-QAM signal. Simulation results show that the power estimation error is within the acceptable level of [Formula: see text][Formula: see text]dB.

scholarly journals An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 73
Author(s):  
Van-Thanh Ta ◽  
Van-Phuc Hoang ◽  
Van-Phu Pham ◽  
Cong-Kha Pham
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
Dynamic Range ◽  
Analog To Digital Converters ◽  
Background Calibration ◽  
Calibration Technique ◽  
Analog To Digital ◽  
Digital Background Calibration ◽  
Field Programmable ◽  
Time Interleaved

The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.

A 10 GB/S EQUALIZER WITH INTEGRATED CLOCK AND DATA RECOVERY FOR OPTICAL COMMUNICATION SYSTEMS

2005 ◽  
Vol 15 (03) ◽  
pp. 525-548 ◽  
Author(s):  
D. S. MCPHERSON ◽  
H. TRAN ◽  
P. POPESCU
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
Automatic Gain Control ◽  
Polarization Mode Dispersion ◽  
Gain Control ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Decision Feedback ◽  
Bicmos Technology ◽  
Feedforward Equalizer

A 10 Gb/s analog continuous-time equalizer with integrated clock and data recovery circuit is presented. It is designed to recover signals degraded by chromatic and polarization mode dispersion. The key components in the design are a feedforward equalizer and a decision feedback equalizer, the parameters of which are electronically adjustable. Both circuit blocks are fully described and characterized with emphasis on minimizing self-induced distortion and maximizing high-speed performance. In addition to the equalizer and the clock and data recovery, the circuit also includes an integrated automatic gain control. The circuit is implemented in a commercial 0.18 μm SiGe BiCMOS technology and consumes 900 mW. The capacity of the equalizer to mitigate signal impairments is demonstrated using three electrically generated channels.

scholarly journals An Overview of Signal Processing Techniques for Terahertz Communications

2020 ◽  
Author(s):  
Hadi Sarieddeen ◽  
Mohamed-Slim Alouini ◽  
Tareq Y. Al-Naffouri
Keyword(s):  
Signal Processing ◽  
Channel Coding ◽  
Communication Systems ◽  
Channel Model ◽  
Mimo Systems ◽  
Future Generation ◽  
Data Detection ◽  
Wide Range ◽  
Processing Techniques ◽  
Signal Processing Techniques

Terahertz (THz)-band communications are a key enabler for future-generation wireless communication systems that promise to integrate a wide range of data-demanding applications. Recent advancements in photonic, electronic, and plasmonic technologies are closing the gap in THz transceiver design. Consequently, prospect THz signal generation, modulation, and radiation methods are converging, and the corresponding channel model, noise, and hardware-impairment notions are emerging. Such progress paves the way for well-grounded research into THz-specific signal processing techniques for wireless communications. This tutorial overviews these techniques with an emphasis on ultra-massive multiple-input multiple-output (UM-MIMO) systems and reconfigurable intelligent surfaces, which are vital to overcoming the distance problem at very high frequencies. We focus on the classical problems of waveform design and modulation, beamforming and precoding, index modulation, channel estimation, channel coding, and data detection. We also motivate signal processing techniques for THz sensing and localization.

scholarly journals CHARACTERISTICS OF DIGITAL AGC IN FIXED-POINT OPERATIONS

2019 ◽  
pp. 5-12
Author(s):  
A. A. Prasolov
Keyword(s):  
Fixed Point ◽  
Communication Systems ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Control Signal ◽  
Reference Level ◽  
Programmable Logic ◽  
Fixed Point Arithmetic ◽  
Digital Receivers ◽  
Point Arithmetic

Introduction. Nowadays, communication systems are mostly digital. One of the tasks of automatic gain control in digital receivers is to maintain analog signals at the appropriately fixed level, which prevents saturation of the analogto-digital converter. Most numerical algorithms are based on floating point arithmetic, and digital automatic gain control is usually implemented using fixed-point arithmetic devices such as programmable logic chips and signal processors. As consequence of fixed-point arithmetic and hardware constraints usage, the out-put significant bits should be truncated correctly. Although many studies mention digital automatic gain control, its characteristics are not considered in detail in terms of the finite capacity of calculators.Objective. The purpose of the study is to analyze dynamic characteristics of digital automatic gain control implemented on a computer for operations on numbers with fixed-point.Materials and methods. Within the frames of the study in Matlab software was developed a mathematical model of digital automatic gain control. The model was implemented on a programmable logic chip.Results. The paper shows the difference in characteristics and features of the digital automatic gain control during operations on fixed-point numbers. The study provides the assessment of the effect of fixed-point signals on the stability of the digital automatic gain control and includes the analysis of causes of spurious oscillations of the control signal.Conclusion. The study proposes the algorithm for compensation of the control signal oscillations by means of correction of the reference level of the digital automatic gain control. Further is required to verify the proposed algorithm on real signals. The results of the study are relevant in development of digital receivers for communication systems of various purposes.

scholarly journals On The Performance Of 1-Bit ADC In Massive MIMO Communication Systems

2020 ◽  
Author(s):  
Hung N Dang ◽  
Thuy Van Nguyen ◽  
Hieu Trung Nguyen
Keyword(s):  
Channel Coding ◽  
Massive Mimo ◽  
Communication Systems ◽  
Mimo Systems ◽  
Rational Solution ◽  
Multiple Input Multiple Output ◽  
Analog To Digital ◽  
Input Multiple Output ◽  
Negative Effect ◽  
Hardware Costs

Massive multiple-input multiple-output (MIMO) with low-resolution analog-to-digital converters is a rational solution to deal with hardware costs and accomplish optimal energy efficiency. In particular, utilizing 1-bit ADCs is one of the best choices for massive MIMO systems. This paper investigates the performance of the 1-bit ADC in the wireless coded communication systems where the robust channel coding, protograph low-density parity-check code (LDPC), is employed. The investigation reveals that the performance of the conventional 1-bit ADC with the truncation limit of 3-sigma is severely destroyed by the quantization distortion even when the number of antennas increases to 100. The optimized 1-bit ADC, though having substantial performance gain over the conventional one, is also affected by the quantization distortion at high coding rates and low MIMO configurations. Importantly, the investigation results suggest that the protograph LDPC codes should be re-designed to combat the negative effect of the quantization distortion of the 1-bit ADC.

Seismic noise‐reduction techniques for use with vertical stacking: An empirical comparison

Geophysics ◽  
1987 ◽  
Vol 52 (3) ◽  
pp. 322-334 ◽  
Author(s):  
Simon L. Klemperer
Keyword(s):  
Noise Reduction ◽  
Ambient Noise ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Noise Levels ◽  
Data Set ◽  
Reduction Techniques ◽  
Noise Rejection ◽  
Wide Range ◽  
Low Levels

A systematic comparison of a wide range of noise‐reduction techniques applied to a single data set collected for this purpose was attempted. The study includes a comparison of the relative benefits of noise‐reduction schemes for very different noise levels. The comparisons use computer simulations of field techniques for noise reduction as applied to deep crustal, 48-fold VIBROSEIS® data. The noise‐reduction techniques involve amplitude scaling (diversity stacking and automatic gain control), noise editing (the use of fixed‐gain and self‐updating noise‐rejection systems with and without buffered memory for recursive editing), and reduced numbers of recording bits (mantissa‐only and sign‐bit‐only formats). The effectiveness of each noise‐reduction procedure is assessed by a study of its effects on noise levels seen on source‐point gathers and on both true‐amplitude and amplitude‐balanced common‐midpoint (CMP) stacks. For low levels of ambient noise, true‐amplitude CMP stacks can be substantially improved by the appropriate noise‐reduction techniques, but CMP stacks incorporating gain control before CMP stacking show only minor improvements. In contrast, when a high level of ambient noise is present, both true‐amplitude and gain‐controlled CMP stacks can be greatly improved by appropriate noise‐reduction processing before vertical stacking. Of procedures involving zeroing of noise bursts, self‐updating noise‐rejection systems were more effective than fixed‐gain noise‐rejection systems for all the conditions simulated here. A system incorporating recursive editing techniques is still more effective at low levels of ambient noise, but this system tends to edit recorded traces too severely at very high noise levels. Mantissa‐only and sign‐bit‐only recording give very similar results, and show an effect comparable to that given by self‐updating editing systems. Diversity stacking produced significant noise reduction in all conditions studied, and may be the most widely applicable and most generally useful of the noise‐reduction methods studied here. ®Trade and service mark of Conoco Inc.

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