scholarly journals Estimation and Analysis of Higher-Order Harmonics in Advanced Integrated Circuits to Implement Noise-Free Future-Generation Micro- and Nanoelectromechanical Systems

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 541
Author(s):  
Muhammad Imran Khan ◽  
Ahmed S. Alshammari ◽  
Badr M. Alshammari ◽  
Ahmed A. Alzamil
Keyword(s):  
Integrated Circuits ◽  
Frequency Band ◽  
Future Generation ◽  
Higher Order ◽  
Nanoelectromechanical Systems ◽  
Model Quality ◽  
Flip Flop ◽  
Transistor Model ◽  
Spectrum Generation ◽  
Time Fall

This work deals with the analysis of spectrum generation from advanced integrated circuits in order to better understand how to suppress the generation of high harmonics, especially in a given frequency band, to design and implement noise-free systems. At higher frequencies, the spectral components of signals with sharp edges contain more energy. However, current closed-form expressions have become increasingly unwieldy to compute higher-order harmonics. The study of spectrum generation provides an insight into suppressing higher-order harmonics (10th order and above), especially in a given frequency band. In this work, we discussed the influence of transistor model quality and input signal on estimates of the harmonic contents of switching waveforms. Accurate estimates of harmonic contents are essential in the design of highly integrated micro- and nanoelectromechanical systems. This paper provides a comparative analysis of various flip-flop/latch topologies on different process technologies, i.e., 130 and 65 nm. An FFT plot of the simulated results signifies that the steeper the spectrum roll-off, the lesser the content of higher-order harmonics. Furthermore, the results of the comparison illustrate the improvement in the rise time, fall time, clock-Q delay and spectrum roll-off on the better selection of slow-changing input signals and more accurate transistor models.

Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation

2008 ◽  
Author(s):  
T. Kiyan ◽  
C. Boit ◽  
C. Brillert
Keyword(s):  
Laser Pulse ◽  
Integrated Circuits ◽  
Continuous Wave ◽  
Fault Injection ◽  
Scan Design ◽  
Flip Flop ◽  
Laser Stimulation ◽  
Scan Chain ◽  
P Type ◽  
Scan Pattern

Abstract In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

2015 ◽  
Vol 24 (07) ◽  
pp. 1550094 ◽  
Author(s):  
Jizhong Shen ◽  
Liang Geng ◽  
Xuexiang Wu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Clock Cycle ◽  
Control Technique ◽  
Switching Activity ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Deep Impact ◽  
Power Pulse

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

scholarly journals Efficient and Compact SR-flip Flop Optical Memory Based Photonic Crystals Platform

2021 ◽  
Author(s):  
Amr Hassan ◽  
Nihal F. F. Areed ◽  
Salah S. A. Obayya ◽  
Hamdi El Mikati
Keyword(s):  
Integrated Circuits ◽  
Optical Memory ◽  
Logic Gates ◽  
Power Input ◽  
Small Dimension ◽  
Square Lattice ◽  
Optical Logic ◽  
Flip Flop ◽  
Compact Size ◽  
Multiple Devices

Abstract The paper presents a different type of designing methods and operational improvements of the optical logic memory SR-flip flop (SR-FF). The proposed optical memory SR-FF is based on two optical NOR logic gates which use two-dimension (2D) photonic crystal (PhC) with a square lattice of silicon (Si) dielectric rods. The structure has a switching time in only a few Picoseconds with little power input and very little power loss. The proposed optical memory SR-FF has a small dimension 38x22 μm2 which makes it one of the best optimized and most practical structures to be used in all photonic integrated circuits (PICs). The ultra-compact size enables the possibility of multiple devices to be embedded in a single PIC chip.

scholarly journals Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1550011
Author(s):  
Neeraja Jagadeesan ◽  
B. Saman ◽  
M. Lingalugari ◽  
P. Gogna ◽  
F. Jain
Keyword(s):  
Integrated Circuits ◽  
Quantum Well ◽  
Logic Gates ◽  
Digital Integrated Circuits ◽  
Short Channel ◽  
Flip Flop ◽  
Coupled Channels ◽  
Threshold Voltages ◽  
Sequential Logic ◽  
Quantum Well Devices

The spatial wavefunction-switched field-effect transistor (SWSFET) is one of the promising quantum well devices that transfers electrons from one quantum well channel to the other channel based on the applied gate voltage. This eliminates the use of more transistors as we have coupled channels in the same device operating at different threshold voltages. This feature can be exploited in many digital integrated circuits thus reducing the count of transistors which translates to less die area. The simulations of basic sequential circuits like SR latch, D latch and flip flop are presented here using SWSFET based logic gates. The circuit model of a SWSFET was developed using Berkeley short channel IGFET model (BSIM 3).

scholarly journals Novel Graphitic Structures by Design

2007 ◽  
Author(s):  
Jonathon Phillips ◽  
Zayd C. Leseman ◽  
Joseph Cordaro ◽  
Claudia Luhrs ◽  
Marwan Al-Haik
Keyword(s):  
Integrated Circuits ◽  
Future Generation ◽  
Single Step ◽  
Three Dimensions ◽  
Laboratory Equipment ◽  
Alternative Technologies ◽  
Novel Technology ◽  
Graphite Structure ◽  
Graphite Growth

Graphitic Structures by Design (GSD) is a novel technology for growing graphite in precise patterns from the nano to the macroscale, rapidly (>1 layer/sec), at low temperatures (ca. 500°C), and in a single step using ordinary laboratory equipment. The GSD process consists of exposing particular metals (Ni, Pd, Pt, Co), which act as ‘templates’, to a fuel rich combustion environment. As an example, we have thoroughly characterized graphite growth on nickel in a mixture of ethylene and oxygen (O2/C2H4 ratio<3), and found that it grows in a geometry remarkably consistent with the shape of the metal template at a rate of the order one graphene layer/second at temperatures between about 500 and 700°C. Graphite structures created with GSD to date include two dimensional ‘screens’ that are inches in extent, yet are composed of micron scale squares graphite foam, hollow nanoparticles, and micron scale particles. All alternative technologies for graphite growth require specialty equipment, such as 2000 °C + ovens, and multiple steps. The alternatives are also not suited for a wide variety of pattern growth in either two or three dimensions. We propose to change focus from demonstrating GSD to determination of the mechanism of graphite growth. GSD could meet a number of recognized technological needs for future generation integrated circuits (IC). Precise patterns of oriented graphite are envisioned as: i) replacements of carbon fibers as structural elements in some aerospace and transport applications, ii) as heat conductive pathways aiding thermal management in ICs iii) as electrical conduits in ICs, iv) as the basic elements of nano-scale logic circuits. GSD graphite is arguably superior to the older and more broadly studied carbon nanotubes technology for all these IC applications for many reasons: only GSD be grown in any pattern on any surface, GSD is far cleaner (no metal residue in the graphite structure, in contrast to nanotubes), GSD structures can be formed consistently and cheaply, at low temperature, and only GSD can be readily grown into large designed macrostructures required for some heat transfer applications.

scholarly journals STDFF A PASS TRANSISTOR BASED FLIP FLOP DESIGN FOR EFFICIENT INTEGRATED CIRCUITS

2014 ◽  
pp. 263-266
Author(s):  
G. LAKSHMI PRANEETHA ◽  
P. HAREESH
Keyword(s):  
Integrated Circuits ◽  
The Other ◽  
New Technique ◽  
Analysis Software ◽  
Flip Flop ◽  
Negative Edge ◽  
Switching Transistor ◽  
Look Ahead ◽  
Pass Transistor ◽  
A New Technique

In this paper a new technique is proposed based on the comparison between Conventional Transistorized Flip-flop and Data transition Look ahead D flip flop here we are checking the working of DLDFF and the conventional D Flip-flop after that we are analyzing the characteristic comparison using power & area constraints after that we are proposing a Negative Edge triggered flip-flop named as Switching Transistor based D Flip-Flop(STDFF) with reduced number of transistors which will reduce the overall power area as well as delay. The simulations are done using Microwind & DSCH analysis software tools and the result between all those types are listed below. Our proposed system simulations are done under 50nm technology and the results are tabulated below. In that our proposed system is showing better output than the other flip-flops compared here.

scholarly journals A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 633
Author(s):  
Dam Minh Tung ◽  
Nguyen Van Toan ◽  
Jeong-Gun Lee
Keyword(s):  
Integrated Circuits ◽  
Error Detection ◽  
Error Resilience ◽  
Cycle Performance ◽  
Timing Error ◽  
Worst Case ◽  
Flip Flop ◽  
Error Detection And Correction ◽  
Field Programmable ◽  
Performance Penalty

Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

100 years multivibrator-history, circuits and mathematical analysis

2020 ◽  
Vol 39 (3) ◽  
pp. 725-737
Author(s):  
Wolfgang Mathis
Keyword(s):  
Integrated Circuits ◽  
Electronic Circuit ◽  
Electrical Circuit ◽  
Nonlinear Circuits ◽  
Mathematical Concepts ◽  
Flip Flop ◽  
Content Type ◽  
History Of ◽  
New Type ◽  
The One

Purpose This work is intended to historically commemorate the one hundredth anniversary of the invention of a new type of electronic circuit, referred to in 1919 by Abraham and Bloch as a multivibrator and by Eccles and Jordan as a trigger relay (later known as a flip-flop). Design/methodology/approach The author also considers the circuit-technical side of this new type of circuit, considering the technological change as well as the mathematical concepts developed in the context of the analysis of the circuit. Findings The multivibrator resulted in a “circuit shape” which became one of the most applied nonlinear circuits in electronics. It is shown that at the beginning the multivibrator as well as the flip-flop circuits were used because their interesting properties in the frequency domain. Originality/value Therefore, it is a very interesting subject to consider the history of the multivibrator as electronic circuits in different technologies including tube, transistors and integrated circuits as well as the mathematical theory based on the concept from electrical circuit theory.

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