scholarly journals A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

2011 ◽  
Vol 2011 ◽  
pp. 1-10 ◽  
Author(s):  
Indranil Hatai ◽  
Indrajit Chakrabarti
Keyword(s):  
Software Defined Radio ◽  
High Speed ◽  
High Performance ◽  
Frequency Synthesizer ◽  
Dynamic Range ◽  
Fpga Implementation ◽  
Clock Frequency ◽  
System Clock ◽  
Quarter Wave ◽  
The Individual

This paper deals with an FPGA implementation of a high performance FM modulator and demodulator for software defined radio (SDR) system. The individual component of proposed FM modulator and demodulator has been optimized in such a way that the overall design consists of a high-speed, area optimized and low-power features. The modulator and demodulator contain an optimized direct digital frequency synthesizer (DDFS) based on quarter-wave symmetry technique for generating the carrier frequency with spurious free dynamic range (SFDR) of more than 64 dB. The FM modulator uses pipelined version of the DDFS to support the up conversion in the digital domain. The proposed FM modulator and demodulator has been implemented and tested using XC2VP30-7ff896 FPGA as a target device and can operate at a maximum frequency of 334.5 MHz and 131 MHz involving around 1.93 K and 6.4 K equivalent gates for FM modulator and FM demodulator respectively. After applying a 10 KHz triangular wave input and by setting the system clock frequency to 100 MHz using Xpower the power has been calculated. The FM modulator consumes 107.67 mW power while FM demodulator consumes 108.67 mW power for the same input running at same data rate.

scholarly journals VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

2012 ◽  
pp. 40-46
Author(s):  
Mr.M.V. Sathish ◽  
Mrs. Sailaja
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Hybrid Type ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

scholarly journals A Novel Highly Linear Voltage-To-Time Converter (VTC) Circuit for Time-Based Analog-To-Digital Converters (ADC) Using Body Biasing

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2033
Author(s):  
Ahmed Elgreatly ◽  
Ahmed Dessouki ◽  
Hassan Mostafa ◽  
Rania Abdalla ◽  
El-sayed El-Rabaie
Keyword(s):  
Power Consumption ◽  
Software Defined Radio ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
The Body ◽  
Analog To Digital Converters ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Operation Speed

Time-based analog-to-digital converter is considered a crucial part in the design of software-defined radio receivers for its higher performance than other analog-to-digital converters in terms of operation speed, input dynamic range and power consumption. In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These novel converters exhibit better linearity, which is analytically proven in this paper. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800 mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology. These novel designs consist of only a single inverter stage, which results in reducing the layout area and the power consumption. The overall power consumption is 18 μW for the first proposed circuit and 15 μW for the second proposed circuit. The novel converter circuits have a resolution of 5 bits and operate at a maximum clock frequency of 500 MHz.

scholarly journals Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Salah Hasan Ibrahim ◽  
Sawal Hamid Md. Ali ◽  
Md. Shabiul Islam
Keyword(s):  
High Speed ◽  
Frequency Synthesizer ◽  
Logic Gates ◽  
Sine Wave ◽  
Lookup Table ◽  
Frequency Resolution ◽  
Digital Frequency ◽  
Quarter Wave ◽  
Direct Digital Frequency Synthesizer ◽  
Gated Clock

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

scholarly journals High Speed Microactuators for Low Aspect Ratio High Speed Micro Aircraft Surfaces

Actuators ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 265
Author(s):  
Ronald Barrett-Gonzalez ◽  
Nathan Wolf
Keyword(s):  
Aspect Ratio ◽  
Flight Control ◽  
High Speed ◽  
High Performance ◽  
Dynamic Range ◽  
Feedback System ◽  
Analytical Models ◽  
Control Surface ◽  
Operational Environment ◽  
Low Aspect Ratio

This paper covers a class of actuators for modern high speed, high performance subscale aircraft. The paper starts with an explanation of the challenges faced by micro aircraft, including low power, extremely tight volume constraints, and high actuator bandwidth requirements. A survey of suitable actuators and actuator materials demonstrates that several classes of piezoceramic actuators are ideally matched to the operational environment. While conventional, linear actuation of piezoelectric actuators can achieve some results, dramatic improvements via reverse-biased spring mechanisms can boost performance and actuator envelopes by nearly an order of magnitude. Among the highest performance, low weight configurations are post-buckled precompressed (PBP) actuator arrangements. Analytical models display large deflections at bandwidths compatible with micro aircraft flight control speed requirements. Bench testing of an example PBP micro actuator powered low aspect ratio flight control surface displays +/−11° deflections through 40 Hz, with no occupation of volume within the aircraft fuselage and good correlation between theory and experiment. A wind tunnel model of an example high speed micro aircraft was fabricated along with low aspect ratio PBP flight control surfaces, demonstrating stable deflection characteristics with increasing speed and actuator bandwidths so high that all major aeromechanical modes could be easily controlled. A new way to control such a PBP stabilator with a Limit Dynamic Driver is found to greatly expand the dynamic range of the stabilator, boosting the dynamic response of the stabilator by more than a factor of four with position feedback system engaged.

scholarly journals IMPLEMENTATION OF A REDUCED COMPLEXITY HIGH PERFORMANCE DATA ACQUISITION CHIP USING 0.18 MICRON TECHNOLOGY

2021 ◽  
Vol 7 (3) ◽  
pp. 22-26
Author(s):  
Hai P. Le ◽  
◽  
Aladin Azyegh ◽  
Jugdutt Singh ◽  
◽  
...  
Keyword(s):  
Low Power ◽  
Data Acquisition ◽  
High Speed ◽  
High Performance ◽  
Modern Science ◽  
Digital Data ◽  
Clock Frequency ◽  
Flash Adc ◽  
Analog Signals ◽  
Wide Range

Data acquisition (DAQ) in the general sense is the process of collecting information from the real world. For engineers and scientists, this data is mostly numerical and is usually collected, stored and analysed using computers. However, most of the input signals cannot be read directly by digital computers. Because they are generally analog signals distinguished by continuous values, while computers can only recognise digital signals containing only the on/off levels. DAQ systems are therefore inevitably necessary, as they include the translation requirements from analog signals to digital data. For this reason, they have become significant in wide range of applications in modern science and technology [1]. The paper precents the disign of a 12-bit high-speed low-power Data Acquisition (DAQ) Chip. In this paper, the disigns of the building block components are aimed at high-accuracy along with high-speed and low power dissipation. A modifided flash Analog-to-Digital converter (ADC) was used instead of the traditional flash proposed DAQ chip operates at 1 GHz master clock frequency and achieves a sampling speed of 125 MS/s. It dissipates only 64.9 mW of power as compared to 97.2 mW when traditional flash ADC was used.

The application of new technologies in the water treatment process of a modern waterworks

2002 ◽  
Vol 2 (1) ◽  
pp. 63-69 ◽  
Author(s):  
O. Hoyer ◽  
J. Clasen
Keyword(s):  
Water Treatment ◽  
High Speed ◽  
High Performance ◽  
Treatment Process ◽  
New Technologies ◽  
Water Treatment Process ◽  
Lime Water ◽  
Aggregation Step ◽  
The Individual ◽  
Filter Bed

The new plant for the treatment of water from the Wahnbach-reservoir went into operation at Siegburg, Germany in 2001. It will have a capacity of 3,600 to 4,800 m3/h and is intended for drinking water supply of the Bonn region. The relatively simple water treatment process achieves its high performance and safety from the sophisticated process layout and control developed from 40 years of research and experience at the Wahnbach Reservoir Association. According to temporal needs permanganate and/or powdered activated carbon can be applied for pretreatment. Flocculation is either possible with Al3+- or Fe3+-salt solutions introduced by optimized flash-mixing and destabilization. Immediately afterwards at the inlet into the 12 aggregation and filtration trains it is possible to inactivate motile planktonic organisms by means of cavitation fields generated by ultrasound at 40 kHz. In the following aggregation step flocs are generated tailored to optimum retention in the double media filters which are regenerated via high speed build-up backwashing. Release of plankton and microorganisms accumulated in the filter bed by motile plankton is inhibited by the ultrasound treatment. A continuously high filtrate quality is achieved by stacked filter-runs of the 12 filters adapted to the water quality with backwashes graded at equal time intervals after identical filter-run times, a filter to waste period after backwash first filtrate separation and permanent turbidity monitoring at the individual filtrate outlets. Disinfection is achieved with 3 closed UV-systems equipped, performance tested and certified according to the DVGW technical standard W 294 and is followed by conventional. de-acidification with addition of lime water. The paper will describe and explain the process concept which has been worked out and validated by WTV within the framework of several research projects.

AFBV: A High-Performance Network Flow Classification Method for Multi-Dimensional Fields and FPGA Implementation

2019 ◽  
Vol 28 (14) ◽  
pp. 1950237
Author(s):  
Ling Zheng ◽  
Zhiliang Qiu ◽  
Weina Wang ◽  
Weitao Pan ◽  
Shiyong Sun ◽  
...  
Keyword(s):  
High Throughput ◽  
Network Flow ◽  
High Speed ◽  
High Performance ◽  
Clock Frequency ◽  
Pipeline Architecture ◽  
Exact Matching ◽  
Flow Classification ◽  
Rule Sets ◽  
Bit Vector

Network flow classification is a key function in high-speed switches and routers. It directly determines the performance of network devices. With the development of the Internet and various kinds of applications, the flow classification needs to support multi-dimensional fields, large rule sets, and sustain a high throughput. Software-based classification cannot meet the performance requirement as high as 100 Gbps. FPGA-based flow classification methods can achieve a very high throughput. However, the range matching is still challenging. For this, this paper proposes a range supported bit vector (RSBV) method. First, the characteristic of range matching is analyzed, then the rules are pre-encoded and stored in memory. Second, the fields of an input packet header are used as addresses to read the memory, and the result of range matching is derived through pipelined Boolean operations. On this basis, bit vector for any types of fields (AFBV) is further proposed, which supports the flow classification for multi-dimensional fields efficiently, including exact matching, longest prefix matching, range matching, and arbitrary wildcard matching. The proposed methods are implemented in FPGA platform. Through a two-dimensional pipeline architecture, the AFBV can operate at a high clock frequency and can achieve a processing speed of more than 100 Gbps. Simulation results show that for a rule set of 512-bit width and 1[Formula: see text]k rules, the AFBV can achieve a throughput of 520 million packets per second (MPPS). The performance is improved by 44% compared with FSBV and 30% compared with Stride BV. The power consumption is reduced by about 43% compared with TCAM solution.

scholarly journals Design of interfaces between high speed data converters and high performance FPGAs for software defined radio applications

2019 ◽  
Vol 71 (4) ◽  
pp. 601-614 ◽  
Author(s):  
Mahadevan Balakrishnan ◽  
Khalim Amjad Meerja ◽  
Kishore Kumar Gundugonti ◽  
Sri Rama Krishna Kalva
Keyword(s):  
Software Defined Radio ◽  
High Speed ◽  
High Performance ◽  
Data Converters ◽  
High Speed Data

Design of Low Power CMOS Comparator using 180nm Technology for ADC Application

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 11-13
Author(s):  
Truptimayee Behera ◽  
Ritisnigdha Das
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Input Voltage ◽  
Clock Frequency ◽  
Nmos Transistor ◽  
Body Effect ◽  
Low Power Dissipation ◽  
Low Power Cmos

In our design of CMOS comparator with high performance using GPDK 180nm technology we optimize these parameters. We analyse the transient response of the schematic design and the gain is calculated in AC analysis and also we measure the power dissipation. The circuit is built by using PMOS and NMOS transistor with a body effect. A plot of phase and gain also discussed in the paper. Finally a test schematic is built and transient analysis for an input voltage of 2V is measured using Cadence virtuoso. Simulation results are presented and it shows that this design can work under high speed clock frequency 200MHz. The design has low power dissipation.

scholarly journals Multiple Use SiPM Integrated Circuit (MUSIC) for Large Area and High Performance Sensors

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 961
Author(s):  
Sergio Gómez ◽  
David Sánchez ◽  
Joan Mauricio ◽  
Eduardo Picatoste ◽  
Andreu Sanuy ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Dynamic Range ◽  
Single Photon ◽  
Experimental Tests ◽  
Output Pulse ◽  
Multiple Use ◽  
Large Area ◽  
The Individual ◽  
Output Driver

The 8-channel Multiple Use Silicon Photo-multiplier (SiPM) Integrated Circuit (MUSIC) Application specific integrated circuit (ASIC) for SiPM anode readout has been designed for applications where large photo-detection areas are required. MUSIC offers three main features: (1) Sum of the eight input channels using a differential output driver, (2) eight individual single ended (SE) analog outputs, and (3) eight individual SE binary outputs using a time over threshold technique. Each functionality, summation and individual readout includes a selectable dual-gain configuration. Moreover, the signal sum implements a dual-gain output providing a 15-bit dynamic range. The circuit contains a tunable pole zero cancellation of the SiPM recovery time constant to deal with most of the available SiPM devices in the market. Experimental tests show how MUSIC can linearly sum signals from different SiPMs and distinguish even a few photons. Additionally, it provides a single photon output pulse width at half maximum (FWHM) between 5–10 ns for the analog output and a single-photon time resolution (SPTR) around 118 ps sigma using a Hamamatsu SiPM S13360-3075CS for the binary output. Lastly, the summation mode has a power consumption of ≈200 mW, whereas the individual readout consumes ≈30 mW/ch.

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